1. Field of the Invention
The present invention relates to a method of and a system for data transmission, employing trellis coded modulation and more particularly to a method of and a system for data transmission through a convolutional encoder, a Viterbi decoder, and a multiphase or multilevel digital radio modulator/demodulator to achieve a constant modulation rate that remains unchanged even if the information rate is increased.
2. Description of the Related Art
Generally, multiphase phase modulation or multilevel amplitude modulation allows 2.sup.N signal points to be provided if the symbol of one signal point is N bits. By adding one redundancy bit, for example, to each N-bit symbol, there are available 2.sup.N+1 signal points arranged in two-dimensional space, and hence the number of signal points is doubled. The set of 2.sup.N+1 signal points is divided so that the Euclidean distance between any two signal points belonging to a subset is larger than the Euclidean distance between any two signal points in different subsets. To encode the signal points, a corresponding subset is selected using the state transition of a finite-state memory based on the transition between states so that only some sequences of signal points are effective. To decode the thus encoded signal sequences in a receiver, there is employed a Viterbi algorithm known as the maximum likelihood decoding process.
Heretofore, as shown in FIG. 6 of the accompanying drawings, a data transmission system of the type described above includes a transmitter comprising convolutional encoder 41, mapping circuit 42 for setting an arrangement of signal points, and 8-PSK (phase shift keying) modulator 43 for phase-modulating which is supplied with 8 signal points generated by 2.sup.3 bits, and a receiver comprising 8-PSK demodulator 44 and Viterbi decoder 45. Convolutional encoder 41 produces output signal points Y.sub.2, Y.sub.1, Y.sub.0 that are mapped into the position shown in FIG. 4 of the accompanying drawings by mapping circuit 42 and then modulated by 8-PSK modulator 43 for transmission to a transmission path. The 8-phase-modulated signal, which contains noise added during transmission, is demodulated into m-bit soft decision I channel, Q channel (I-ch., Q-ch.) data by 8-PSK demodulator 44. The m-bit soft decision I-ch., Q-ch. data are supplied to Viterbi decoder 45, which produces estimated information data d.
Operation of convolutional encoder 41 will be described below with reference to FIG. 12 of the accompanying drawings. Convolutional encoder 41 is supplied with parallel information bits X.sub.1, X.sub.2 that have been converted by serial/parallel converter 101 connected to input terminals 77, 78 of convolutional encoder 41. If the encoding ratio is 2/3, then exclusive-OR gates 85, 86 of convolutional encoder 41 output exclusive-OR of information bits X.sub.1, X.sub.2 supplied from input terminals 77, 78 and output signals from shift registers 82, 83, and are stored in respective shift registers 83, 84. At this point, convolutional encoder 41 outputs, as coded data, output signals Y.sub.1, Y.sub.2 as respective information bits X.sub.1, X.sub.2 and redundancy bit Y.sub.0 from respective output terminals 80, 79, 81. Each time information bits X.sub.1, X.sub.2 are inputted, convolutional encoder 41 repeats the above operation and produces output data Y.sub.1, Y.sub.2, Y.sub.0. Output data Y.sub.1, Y.sub.2, Y.sub.0 are then mapped into the positions shown in FIG. 4 by mapping circuit 42. If information bits X.sub.1, X.sub.2, X.sub.3 inputted and the encoding ratio is 3/4, then, assuming that convolutional encoder 41 is used, convolutional encoder 41 adds redundancy bit Y.sub.0 depending on information bits X.sub.1, X.sub.2 to information bits X.sub.1, X.sub.2, X.sub.3, and produces 4-bit output data. When information bit X.sub.3 is an error-correcting bit, it should not be led into the convolutional encoding. Since one symbol is composed of the data X.sub.1, X.sub.2, X.sub.3, Y.sub.0, the 8 PSK modulator in the data transmission system shown in FIG. 6 cannot be used, and it is necessary to use a 16 QAM modulator adapted to a symbol composed of 4 bits, for example.
Operation of Viterbi decoder 45 will be described below with reference to FIGS. 9, 10, 11, and 13 of the accompanying drawings. FIG. 9 shows the trellis transition of convolutional encoder 41. FIG. 10 shows an ACS (add compare select) circuit composed of adders 50 through 53, comparator 54, and selector 55, and FIG. 11 also shows the ACS circuit. FIG. 13 shows Viterbi decoder 45. In FIG. 13, the m-bit soft decision I ch., Q ch. data decoded from an 8-PSK signal are supplied from input terminals 87, 88, respectively, to branch metric generator 89, which determines likelihood estimates (branch metrics) BM0, BM1, . . . , BM7 between the 8-phase signal points and reception points as shown in FIG. 4. The likelihood estimates BM0, BM1, . . . , BM7 are supplied to ACS circuit 90. To process a 0th state as shown in FIG. 10, branch and path metrics BM0', PM0, branch and path metrics BM2', PM2, branch and path metrics BM4', PM4, and branch and path metrics BM6', PM6 are added by respective adders 50, 51, 52, 53, and a path metric with maximum likelihood is calculated by comparator 54 and selected by selector 55 as a path metric PM0 on the next occasion. It is assumed that a path that has transited from a 4th state is selected. Upon selection of the path, the history data of the path stored in 4th-state shift register 75 (see FIG. 11) in path memory 91 is shifted to the right into 0th-state shift registers 73 by select signals SEL0 applied to selectors 56, 60, 64, 68, so that 0th-state shift registers 73 store two information bits "01" that are a transition output. Similarly, the above operation is simultaneously carried out with respect to the 1st, 2nd, . . . , 7th states by circuits based on the trellis transition shown in FIG. 9. Each time a received symbol is inputted, path metrics PM0.about.PM7 with maximum likelihood are detected by maximum likelihood decider 92, and the output signal from the final shift register which represents the state of the most likelihood path is selected by selector 72, thus producing estimates X.sub.2, X.sub.1 indicative of estimated decoded bits.
With the conventional data transmission system described above, if the encoding ratio is 2/3, then an 8-PSK modulator/demodulator may be used. However, if the encoding ratio is 3/4, then a 16-QAM modulator/demodulator has to be used. Therefore, the conventional coding modulation process cannot employ the same modulator/demodulator when the information rate is increased with the modulation rate being kept constant.